The present invention relates to a pattern layout method of a semiconductor device, particularly a pattern layout method of the semiconductor deice construction of a display driver and the like having an anode driver and a cathode driver for example and making them in one chip.
A semiconductor device constituting the above-mentioned display driver and the like will be described referring a drawing.
In the above-mentioned display, there are various kinds of flat panel displays such as an LCD, an LED display, an organic EL (Electroluminescence) display, an inorganic EL display, a PDP (Plasma Display Panel), an FED (Field Emission Display), and so on.
An organic EL display driver will be described below as an example, which has an anode driver and a cathode driver for example, supplies constant current to the organic EL element, and makes the organic EL element emit light. Since the EL element has many merits such that a back light required in a liquid crystal display is not necessitated because of self-luminescence and that there is not limit about visual field angle, application for display device of next generation is expected. Especially, it is known that the organic EL element is possible in high brightness and superior than an inorganic EL element in high efficiency, high response characteristic, and multiple color.
The above-mentioned organic EL display driver includes logic N-channel MOS transistor and P-channel MOS transistor, N-channel high-voltage MOS transistor and P-channel high-voltage MOS transistor of high withstand voltage, N-channel high-voltage MOS transistor and P-channel high-voltage MOS transistor of high withstand voltage reduced in on-resistance, N-channel MOS transistor for a level shifter, and so on. Here, a DMOS (Double-diffused Metal-Oxide Semiconductor) transistor and the like are used for the high-voltage MOS transistor reduced in on-resistance for example. In the above-mentioned DMOS transistor construction, new diffusion region is formed by diffusing impurity different in conductive type to diffusion region formed at surface side of semiconductor substrate and difference of vertical direction diffusion of these diffusion regions is used as effective channel length so that the transistor is an element suitable for low on-resistance by forming short channel.
A pattern layout of a semiconductor device at constituting various kinds of drivers such as the above-mentioned the organic EL display driver has constitution where required numbers of output of layouts for one bit output are arranged repeatedly.
Here, an anode driver, a cathode driver, a memory portion, and the like are constituted separately at constitution of the above-mentioned organic EL display driver. Because of that, mounting them in one printing board is not satisfied in cost and size.
It is desired to design miniaturization of chip size and low cost by making the anode driver, the cathode driver, the memory portion, and the like in one chip.
Further, in the constitution only arranging various kinds of drivers repeatedly times of necessary number of outputs, space for drawing wiring around and the like is need so as to bring enlargement of chip size.
That is, FIG. 17A is a plane view showing a pattern layout of a semiconductor device constituting for driving display, and layouts for output one bit are arranged repeatedly times of necessary number of outputs as above-mentioned.
Here, numeral 1 in FIG. 17A denotes an output region corresponding to one bit, and a driver portion having desired number of outputs is constituted arranging plural output 3 regions 1 for the one bit. Numeral 2 denotes wiring for a gate electrode formed in the output regions 1, and source region (S) and drain region (D) are formed to be adjacent to the wiring for the gate electrode (See the enlarged figure in the circle of FIG. 17A).
The shape of the wiring 2 for gate electrode shown in FIG. 17A is only an example, and various kinds of wiring for gate electrodes 2B, 2C, and 2D shown in FIGS. 17B, 17C, and 17D may be constituted. The above-mentioned constitution arranging layout for output one bit repeatedly times of necessary number of outputs does not respond to a request for further multi bits at making in one chip because of the problem of inconvenience of drawing wiring around and taking space of drawing it around.
Furthermore, a problem of variation between bits rises as multi bits advance. That is, the variation between bits causes to generate micro-loading effect by difference between fineness and roughness of gate electrode forming pattern, and occasionally finishing shape and working dimension of the gate electrode go wrong by the effect.
Especially, when the organic EL display driver having the anode driver, the cathode driver, and the like as above-mentioned are made in one chip, each driver portion is mounted mixedly naturally. Therefore, the above-mentioned difference between fineness and roughness of the gate electrode forming pattern becomes large, micro-loading effect generates easily at photolithography and etching, variation of finishing shape and working dimension of the gate electrode caused by the effect becomes large, and being out of order in display generates.
According to a first aspect of the present invention, in the pattern layout method of the semiconductor device of the present invention, desired drivers connected to the memory portions are laid out equally in the chip and each memory portion is arranged equally in the vicinity of each driver laid out equally in the semiconductor device made in one chip with an anode driver, a cathode driver, and memory portions.
Preferably, the desired drivers connected to the memory portions are divided into plural groups and each memory portion is arranged in every group.
Further, the desired drivers connected to the memory portions are placed face to face at right and left positions or high and low positions, and each memory portion is arranged at center portion of the chip.
Moreover, the semiconductor constitutes each transistor for a driver and the each dummy pattern is formed to be adjacent to the end portion of the output bit group constituting a cathode driver, an anode driver, and an anode driver for icon.
Further, the dummy pattern is formed at an empty space in a region where the plural output bits are arranged.
Moreover, number of outputs of the dummy pattern formed at a region where output bit groups constituting the cathode driver, the anode driver, and the anode driver for icon are adjacent each other is less than number of outputs of the dummy pattern formed at a region where output bit groups are not adjacent each other.
Further, the dummy pattern has the same shape as wiring for gate electrode.
According to the second aspect of the invention, in the pattern layout method of the semiconductor device, plural output groups are arranged at periphery portion in the chip for drivers where plural output regions corresponding to one bit are arranged to constitute desired output bit group and made in one chip.
Preferably, wiring connected to each output bit arranged at the periphery portion is wired so as to circle fitting shape of the chip.
Further, the pattern layout method of the semiconductor device is applied to display drivers where drivers, memory portions, etc. are made in one chip, and the drivers are arranged at periphery portion in the chip in the state of grouping by every desired output bit group, and wiring connected to each output bit arranged at the periphery portion is wired so as to circle fitting shape of the chip.
Moreover, the drivers are anode drivers and cathode drivers, and the anode drivers or cathode drivers are arranged at periphery portion in the chip in the state of grouping by every desired output bit group, and that wiring connected to each output bit arranged at the periphery portion is wired so as to circle fitting shape of the chip.
Further, the wirings are a power source line and a signal line, and moreover, that the each output bit group is arranged so as to surround the memory portions at the periphery portion.
Moreover, the semiconductor constitutes each transistor for a driver and the each dummy pattern is formed to be adjacent to the end portion of the output bit group constituting a cathode driver, an anode driver, and an anode driver for icon.
Further, the dummy pattern is formed at an empty space in a region where the plural output bits are arranged.
Furthermore, number of outputs of the dummy pattern formed at a region where output bit groups constituting the cathode driver, the anode driver, and the anode driver for icon are adjacent each other is less than number of outputs of the dummy pattern formed at a region where output bit groups are not adjacent each other.
Further, the dummy pattern has the same shape as wiring for gate electrode.